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DKC21.3-200-7-FW
圖4-5和4-6顯示了
WFTRIG信號(hào)。
圖4-5：。WFTRIG輸入信號(hào)定時(shí)
圖4-6：。WFTRIG輸出信號(hào)定時(shí)
更新*信號(hào)
任何PFI引腳都可以從外部輸入更新*信號(hào)，該信號(hào)可用
作為PFI5/更新*引腳上的輸出。
作為輸入，在邊緣檢測(cè)模式下配置更新*信號(hào)。
您可以選擇任何PFI引腳作為更新*的源，并配置
上升沿或下降沿的極性選擇。的選定邊
更新*信號(hào)更新DAC的輸出。為了使用
更新*，則必須將DAC設(shè)置為發(fā)布更新模式。
作為輸出，更新*信號(hào)反映實(shí)際更新脈沖，即
連接到DAC。即使更新是在外部進(jìn)行的，也是如此
由另一個(gè)PFI生成。輸出為激活的低脈沖和脈沖
寬度為50至75 ns。該輸出在啟動(dòng)時(shí)設(shè)置為三態(tài)。

Figures 4-5 and 4-6 show the input and output timing requirements for the WFTRIG signal. Figure 4-5. WFTRIG Input Signal Timing Figure 4-6. WFTRIG Output Signal Timing UPDATE* Signal Any PFI pin can externally input the UPDATE* signal, which is available as an output on the PFI5/UPDATE* pin. As an input, the UPDATE* signal is configured in the edge-detection mode. You can select any PFI pin as the source for UPDATE* and configure the polarity selection for either rising or falling edge. The selected edge of the UPDATE* signal updates the outputs of the DACs. In order to use UPDATE*, you must set the DACs to posted-update mode. As an output, the UPDATE* signal reflects the actual update pulse that is connected to the DACs. This is true even if the updates are being externally generated by another PFI. The output is an active low pulse with a pulse width of 50 to 75 ns. This output is set to tri-state at startup.