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PXI-6652
任何PFI引腳都可以從外部輸入WFTRIG信號(hào)，該信號(hào)可作為PFI6/WFTRIG引腳的輸出。作為輸入，WFTRIG配置為邊緣檢測(cè)模式。您可以選擇任何PFI引腳作為WFTRIG的源，并配置上升沿或下降沿的極性選擇。WFTRIG的選定邊緣開(kāi)始DAC的波形生成。如果選擇內(nèi)部生成的更新*，則會(huì)啟動(dòng)更新間隔計(jì)數(shù)器（UI）。作為輸出，WFTRIG反映啟動(dòng)波形生成的觸發(fā)器，即使波形生成是由另一個(gè)PFI外部觸發(fā)的。輸出為有源高脈沖，脈沖寬度為25至50 ns。該輸出在啟動(dòng)時(shí)設(shè)置為高阻抗。圖4-22和4-23顯示了WFTRIG的定時(shí)要求。圖4-22：。WFTRIG輸入信號(hào)定時(shí)圖4-23。WFTRIG輸出信號(hào)定時(shí)上升沿極性下降沿極性t w t w=10 ns小t w t w=25-50 ns第4章連接信號(hào)©National Instruments Corporation 4-29 NI PCI-6110/6111用戶(hù)手冊(cè)更新*信號(hào)任何PFI引腳都可以從外部輸入更新*信號(hào)，該信號(hào)可作為PFI5/更新*引腳上的輸出。作為輸入，在邊緣檢測(cè)模式下配置更新*。您可以選擇任何PFI引腳作為更新*的源，并為上升沿或下降沿配置極性選擇。選定的更新邊*更新DAC的輸出。要使用更新*，必須將DAC設(shè)置為發(fā)布更新模式。作為輸出，更新*反映連接到DAC的實(shí)際更新脈沖，即使更新是由另一個(gè)PFI外部生成的。輸出為有效低脈沖，脈沖寬度為50至75 ns。該輸出在啟動(dòng)時(shí)設(shè)置為高阻抗。圖4-24和4-25顯示了更新*的時(shí)間要求。圖4-24：。更新*輸入信號(hào)定時(shí)圖4-25。更新*輸出信號(hào)定時(shí)DAC在前緣100 ns內(nèi)更新。用足夠的時(shí)間分離更新*脈沖，以便新數(shù)據(jù)可以寫(xiě)入DAC鎖存器。除非您選擇一些外部源，否則NI PCI-6110/6111UI通常會(huì)生成更新*。WFTRIG信號(hào)啟動(dòng)UI，軟件或內(nèi)部緩沖區(qū)計(jì)數(shù)器可以停止UI。

Any PFI pin can externally input the WFTRIG signal, which is available as an output on the PFI6/WFTRIG pin. As an input, WFTRIG is configured in the edge-detection mode. You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge. The selected edge of WFTRIG starts the waveform generation for the DACs. The update interval counter (UI) is started if you select internally generated UPDATE*. As an output, WFTRIG reflects the trigger that initiates waveform generation, even if the waveform generation is being externally triggered by another PFI. The output is an active high pulse with a pulse width of 25 to 50 ns. This output is set to high-impedance at startup. Figures 4-22 and 4-23 show the timing requirements for WFTRIG. Figure 4-22. WFTRIG Input Signal Timing Figure 4-23. WFTRIG Output Signal Timing Rising-edge polarity Falling-edge polarity t w t w = 10 ns minimum t w t w = 25-50 ns Chapter 4 Connecting Signals © National Instruments Corporation 4-29 NI PCI-6110/6111 User Manual UPDATE* Signal Any PFI pin can externally input the UPDATE* signal, which is available as an output on the PFI5/UPDATE* pin. As an input, UPDATE* is configured in the edge-detection mode. You can select any PFI pin as the source for UPDATE* and configure the polarity selection for either rising or falling edge. The selected edge of UPDATE* updates the outputs of the DACs. In order to use UPDATE*, you must set the DACs to posted-update mode. As an output, UPDATE* reflects the actual update pulse that is connected to the DACs, even if the updates are being externally generated by another PFI. The output is an active low pulse with a pulse width of 50 to 75 ns. This output is set to high-impedance at startup. Figures 4-24 and 4-25 show the timing requirements for UPDATE*. Figure 4-24. UPDATE* Input Signal Timing Figure 4-25. UPDATE* Output Signal Timing The DACs are updated within 100 ns of the leading edge. Separate the UPDATE* pulses with enough time that new data can be written to the DAC latches. The NI PCI-6110/6111UI normally generates UPDATE* unless you select some external source. The WFTRIG signal starts the UI, and the UI can be stopped by software or the internal Buffer Counter.