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PXI-4495
定時(shí)和同步質(zhì)量
PXI系統(tǒng)的一個(gè)關(guān)鍵優(yōu)勢是集成的定時(shí)和同步功能。PXI機(jī)箱
集成了專用的10 MHz系統(tǒng)參考時(shí)鐘、PXI觸發(fā)總線、星形觸發(fā)總線和插槽到插槽
本地總線，而PXI Express機(jī)箱添加了100 MHz差分系統(tǒng)時(shí)鐘、差分信號、，
和差分星形觸發(fā)器，以滿足定時(shí)和同步的需要。
圖8：。PXI Express背板信號布線圖
背板系統(tǒng)參考時(shí)鐘的相位噪聲和穩(wěn)定性是
PXI機(jī)箱，因?yàn)樗鼈儽砻髂梢云谕谙到y(tǒng)內(nèi)同步模塊的可靠性。
在選擇組件和背板設(shè)計(jì)的情況下，PXI Express 100的相位噪聲性能
NI PXI Express機(jī)箱上的MHz差分系統(tǒng)時(shí)鐘性能比
同類其他供應(yīng)商的機(jī)箱。
您可以將10 MHz和100 MHz系統(tǒng)參考時(shí)鐘進(jìn)行鎖相環(huán)（PLL）以獲得更高的穩(wěn)定性
時(shí)鐘源，而不是機(jī)箱背板上提供的時(shí)鐘源。這有助于提高PXI的采樣率
模塊，以便更好地跨多個(gè)儀器對齊其樣本。NI PXI機(jī)箱的PLL電路
設(shè)計(jì)用于在鎖定到外部參考時(shí)抑制更多噪音，從而允許更干凈
傳輸更高穩(wěn)定性的時(shí)鐘源。使用其他供應(yīng)商的機(jī)箱，具體取決于系統(tǒng)
應(yīng)用程序所需的時(shí)鐘源相位噪聲，可能需要外部參考鎖相
單獨(dú)時(shí)鐘到每個(gè)模塊，而不是在系統(tǒng)級時(shí)鐘到機(jī)箱背板，導(dǎo)致
系統(tǒng)復(fù)雜性和成本增加。6.

Timing and Synchronization Quality A key advantage of a PXI system is the integrated timing and synchronization capabilities. A PXI chassis incorporates a dedicated 10 MHz system reference clock, PXI trigger bus, star trigger bus, and slot-to-slot local bus, while a PXI Express chassis adds a 100 MHz differential system clock, differential signaling, and differential star triggers to address the need for advanced timing and synchronization. Figure 8. PXI Express backplane signal routing diagram The phase noise and stability of the backplane system reference clocks are important characteristics of the PXI chassis, as they indicate how reliably you can expect to synchronize modules within the system. Given the choice of components and backplane design, phase noise performance of the PXI Express 100 MHz differential system clock on NI PXI Express chassis has performed orders of magnitude better than other vendors’ chassis in the same class. You can phase-lock-loop (PLL) the 10 MHz and 100 MHz system reference clocks to a higher stability clock source than that which is provided on the chassis backplane. This helps higher-sample-rate PXI modules to better align their samples across multiple instruments. The PLL circuitry of the NI PXI chassis is designed to suppress more noise when locking to an external reference, thus permitting cleaner transmission of the higher stability clock source. With other vendors’ chassis, depending on the system clock source phase noise required by the application, you may need to phase-lock the external reference clock to each module individually rather than at a system level to the chassis backplane, resulting in an increase in system complexity and cost.6